Half-bridge inverters are sufficiently well known for generating an ac voltage from a dc voltage. They are widely used in switched-mode power supplies (SMPS) Since the half-bridge inverter is cost effective with reference to other switched-mode power supply topologies (for example full-bridge inverters), it is dominant, in particular, in cost-sensitive areas such as lighting engineering. Electronic operating units for fluorescent lamps or halogen incandescent lamps are virtually exclusively equipped with half-bridge inverters.
A half-bridge inverter essentially comprises the series circuit of an upper and a lower half-bridge switch that is connected to a power supply that essentially constitutes a dc voltage with a positive pole and a negative pole. This is a rectified line voltage in the simplest case. Provided at the tie point of the half-bridge switches is a half-bridge output voltage UHB which has a substantial ac voltage component and feeds a load circuit that picks a load current IL. In the case of lighting engineering, the load circuit essentially comprises a reactance network with one or more lamps as energy consumers.
In general, two half-bridge switches are designed as electronic switches such as, for example, MOSFET, bipolar transistor or IGBT. For technical reasons relating to semiconductors, it is mostly N channel or NPN transistors that are used in power electronics, for which reason the following statements deal with this type of transistor. However, it is also possible throughout to use transistors complementary thereto. All that need be done is to invert the polarity of the power supply and, where appropriate, the drive of the transistors. In the case of N-channel or NPN-transistors, the upper half-bridge switch is coupled to the positive pole, and the lower transistor is coupled to the negative pole, the negative pole constituting a reference potential for the entire circuit arrangement including the half-bridge inverter. This also explains the designations of upper and lower half-bridge switch: the upper half-bridge switch is at a higher potential than the lower half-bridge switch in relation to the reference potential, at least during the time it is switched on.
It must be avoided in any case that the two half-bridge switches are switched on simultaneously, since otherwise the power supply is short circuited. However, there is inserted between the phases in which one of the two half-bridge switches is switched on a phase in which none of the two half-bridge switches is switched on. This phase is termed dead time in the literature. The dead time has the function not only of creating a safety gap between the switched-on phases of the half-bridge switches, but rather the tie point of the half-bridge switches is to be given the opportunity to change its potential during the dead time. The energy that is stored in the load circuit, and largely in inductive components there, is capable of eliminating, or at least minimizing, the voltage at the half-bridge switch that is switched on after the dead time. Consequently, the relevant half-bridge switch can be switched on without losses or at least with the minimum possible loss. This state of affairs is also denoted in the literature as zero voltage switching (ZVS). The time that passes until the tie point of the half-bridge switches has assumed a potential that ensures minimal switch-on losses is denoted below as the reversal time.
The electronic switches used as half-bridge switches generally have a working electrode (for example drain, collector), a reference electrode (for example source, emitter) and a control electrode (for example gate, base). The control electrode forms a control input of the half-bridge switch. The switch is generally switched on by a drive signal that is present between the control electrode and reference electrode. FIG. 1 illustrates a prior art relating to how the drive signals are provided for the half-bridge switches.
The half-bridge switches T1 and T2 are designed as MOSFETs in FIG. 1. The upper half-bridge switch T1 is connected in series with the lower half-bridge switch T2. The drain terminal of the upper half-bridge switch T1 is connected to the tie point J3, to which the positive pole of the power supply is connected. The source terminal of the lower half-bridge switch T2 is connected to the tie point J1, to which the negative pole of the power supply is connected. As may be seen from FIG. 1, the potential of J1 forms a reference potential for the half-bridge inverter shown. The source terminal of T1 and the drain terminal of T2 are connected and are fed to the tie point J2 that forms the half-bridge output. At J2, the half-bridge inverter supplies a half-bridge output voltage UHB to a load circuit. The driving of the gate terminals of T1 and T2 is described below as it corresponds to the prior art and is illustrated in FIG. 1.
A control module 1 that is supplied with energy via the tie point J4 of an auxiliary voltage supply makes a rectangular control signal available at its control output 2. The form of the control signal corresponds to the inverse of the desired form of the half-bridge output voltage UHB. The control signal can assume a low state and a high state. The intention is that the upper half-bridge switch T1 is switched on in the low state of the control signal, and the lower half-bridge switch T2 is switched on in the high state. The control signal is connected to the gate of the lower half-bridge switch T2 via the parallel circuit of a resistor R1 and a diode D1. Consequently, the voltage value of the control signal in a high state must be at least as great as the gate/source voltage that is required for switching on the lower half-bridge switch T2. The voltage value of the control signal in the low state must be lower than the minimum value that is required for the relevant gate/source voltage for switching on. The resistor R1 effects a switching-on delay for T2 that is bridged by the diode D1 in order to switch off T2.
Providing the drive signal for the upper half-bridge transistor T1 is more complicated, since the reference electrode of T1 is not at the same potential as the reference potential of the control module. In accordance with FIG. 1, an upper drive circuit 3 is provided for the upper half-bridge transistor T1. In the simplest case, this drive circuit comprises a totem pole circuit known from the literature. The output of the upper drive circuit is connected to the gate of the upper half-bridge transistor T1. The energy for the upper drive circuit is fed via the terminals 4 and 5, the terminal 5 also constituting the reference potential for the output of the upper drive circuit, and an operating voltage of the upper drive circuit being required at the terminal 4. The energy supply for the upper drive circuit is implemented by a known pump circuit comprising the capacitor C1 and the diode D2. C1 and D2 are connected in series between the auxiliary voltage supply at the tie point J4 and the half-bridge output at the tie point J2. The energy for the upper drive circuit is drawn from the capacitor C1.
The input of the upper drive circuit 6 is connected via a pull up resistor R2 to the terminal 4 of the upper drive circuit, at which the operating voltage thereof is present. Without further measures, the pull up resistor R2 is led to a control signal for an upper half-bridge transistor that switches the latter on. It is therefore necessary to ensure that the upper half-bridge transistor T1 is switched off in the high state of the control signal from the control module. A level shift switch T3 fulfills this purpose. It is designed in FIG. 1 as a MOSFET whose drain terminal is connected to the input of the upper drive circuit 6, whose gate terminal is connected to the control output of the control module 2, and whose source terminal is connected, via a current negative feedback resistor R3, to the reference potential of the half-bridge inverter. The level shift switch T3 is switched on in the high state of the control signal, as a result of which the voltage at the input of the upper drive circuit 6 is reduced to a value that causes the upper half-bridge transistor T1 to be switched off. The drain terminal of the level shift switch T3 is additionally connected to the half-bridge output J2 via a diode D3. This prevents a current from flowing through the upper drive circuit when the level shift switch T3 is switched on. D3 is preferably designed as a Schottky diode, in order to keep low a forward voltage that occurs. The current negative feedback resistor R3 is intended to limit the current through the level shift switch T3.
In the case of the circuit described, a switching-on delay of the upper half-bridge transistor T1 is provided by virtue of the fact that the Miller capacitance of T3 must be charged via R2 after T3 has been switched off. The upper half-bridge transistor T1 is not switched on until the voltage across this Miller capacitance exceeds a given threshold value at the input 6 of the upper drive circuit. Thus, the desired dead time that passes between switching off the lower half-bridge transistor T2 and switching on the upper half-bridge transistor T1 can be set by the value of the pull up resistor R2.
The switching-on delay for the lower half-bridge transistor T2 cannot be implemented in this way. Only the resistor R1 offers the possibility of modifying the charging time of the gate/source capacitance of the lower half-bridge transistor T2. However, it is possible thereby to realize only dead times that are shorter than the above named reversal time. Longer dead times would cause the lower half-bridge transistor T2 to be operated too long in the so-called linear working range in which very large losses occur.
Document U.S. Pat. No. 5,550,436 (Houk) describes a dead time generation for the transition from the upper to the lower half-bridge transistor by means of a switching-on delay unit (LSDELAY) for the lower half-bridge transistor. However, this solution has two disadvantages: firstly, the said switching-on delay unit forms a part of an integrated circuit, and this means a substantial outlay on costs; secondly the dead time is fixed for a given dimensioning and does not match the above named reversal time. Consequently, the dead time must always be longer than the optimal dead time, and this leads to losses in efficiency of the half-bridge converter.